6001l2

Listing 2. Needs caption

\begin{verbatim}
module test;

   /* Make a reset that pulses once. */
   reg reset = 0;
   initial begin
      # 17 reset = 1;
      # 11 reset = 0;
      # 29 reset = 1;
      # 11 reset = 0;
      # 100 $stop;
   end

   /* Make a regular pulsing clock. */
   reg clk;
   always #5 clk = !clk;

   wire [7:0] value;
   counter c1 (value, clk, reset);


   initial $monitor("At time %t, value = %h (%0d)", $time, value, value);
endmodule // test

\end{verbatim}
\caption{Example Verilog simulation file \texttt{counter2.v}}\label{fig2}

    % iverilog -o a.vvp -ylib counter2.v
    % vvp a.vvp
    [...]