Listing 1. Verlog Source Code for a 16-bit Pipelined Multiplier

module mpy16(p,x,y,clk);
    	output [31:0] p;
    	input [15:0] x;
    	input [15:0] y;
    	input clk;

	// inferrable storage via synthesis
	reg [31:0] p;
	reg [15:0] xq;
	reg [15:0] yq;

	// 16x16 unsigned multiplier specified behaviorally
	always @(posedge clk)
		begin
			xq <= x;
			yq <= y;
			p <= xq * yq;
		end
endmodule // mpy16