6001l1

Listing 1. Needs caption

\begin{verbatim}
module counter(out, clk, reset);

   parameter WIDTH = 8;

   output [WIDTH-1 : 0] out;
   input 	       clk, reset;

   reg [WIDTH-1 : 0]   out;
   wire 	       clk, reset;

   always @(posedge clk)
     out <= out + 1;

   always @reset
     if (reset)
       assign out = 0;
     else
       deassign out;

endmodule // counter

module test;

   /* Make a reset that pulses once. */
   reg reset = 0;
   initial begin
      # 17 reset = 1;
      # 11 reset = 0;
      # 29 reset = 1;
      # 11 reset = 0;
      # 100 $stop;
   end

   /* Make a regular pulsing clock. */
   reg clk;
   always #5 clk = !clk;

   wire [7:0] value;
   counter c1 (value, clk, reset);


   initial $monitor("At time %t, value = %h (%0d)", $time, value, value);
endmodule // test

\end{verbatim}
\caption{Example Verilog simulation file \texttt{counter1.v}}\label{fig1}

    % iverilog -oa.vvp  counter1.v
    % vvp a.vvp
    At time                   17, value = 00 (0)
    At time                   35, value = 01 (1)
    At time                   45, value = 02 (2)
    At time                   55, value = 03 (3)
    At time                   57, value = 00 (0)
    At time                   75, value = 01 (1)
    At time                   85, value = 02 (2)
    At time                   95, value = 03 (3)
    At time                  105, value = 04 (4)
    At time                  115, value = 05 (5)
    At time                  125, value = 06 (6)
    At time                  135, value = 07 (7)
    At time                  145, value = 08 (8)
    At time                  155, value = 09 (9)
    At time                  165, value = 0a (10)